1. Field of the Invention
The invention relates to systems and methods for implementing embedded memory for integrated circuits (ICs). In particular, the invention relates to systems and methods for testing and implementing embedded buffer memory within a high performance network device, such as a switch, wherein such systems and methods include testing the memory for memory failures and identifying the location of the memory failures in order to increase manufacturing yield.
2. Description of the Related Art
Integrated circuits are well known. The proliferation of computer systems is, at least in part, due to advances in designing and manufacturing ICs which allow for smaller and faster computer processor and components. Equally important to the development of computer systems are advances in memory technology which allows the production of faster and smaller memory components, including embedded and external memory devices. Such advances have fostered the competitive development and marketing of computer systems, networks and an extraordinary variety of processor-based devices. Networked computer usage has become so commonplace that it is almost impossible to find an office in the United States that does not employ several LANS (local area networks) used to facilitate its day-to-day business operations. Computer networks may include a variety of high-speed network devices, such as switches or routers, used to relay and route data from one computer station to another.
High-speed network devices like a switch, rely on external and internal (i.e., silicon-embedded) memory for performing various network functions. Competition and other market pressures have required the production of more capable network devices at lower costs. Increased network and device speed is required by customers. One way of increasing the performance of a network device is to increase the speed and reliability of its associated memory. Also, the size and packaging of the memory can effect the performance as well as the cost of the devices. However, reducing the size and increasing the speed of a device can also decrease the reliability of memory devices being mass produced, thereby decreasing the manufacturing yield and increasing the cost of each device. Accordingly, systems and methods for determining and correcting memory failures in memory devices are needed.
For example, it is known that memory failures occur more often in 0.13 μm embedded memory than compared to the rate of failure of 0.18 μm embedded memory. One way to achieve a low cost of manufacturing is to reduce the number of failures caused by the manufacturing process, which increases the manufacturing yield. One way for correcting memory failures in such memory devices is to use memory redundancy. For example, referring to FIG. 1, a system 100 may include a buffer memory 102 and a memory controller 104. Due to the reduced size of the buffer memory 102, memory failures may occur in certain rows of buffer memory 102. Accordingly, additional rows may be added during manufacturing as redundant memory. A plurality of fuses 108A may be added to system 100, which are used to selectively enable redundant memory rows as required. These fuses are connected to each redundant memory row and can store the location address of a failed memory address. A wafer test may be performed on the system to determine which rows of buffer memory 102 have failed. Then, the appropriate fuse of the plurality of fuses 108A can be blown in order to activate a redundant row to replace the failed row, thereby correcting the failure. Therefore, at a low cost, a small amount of redundant rows may be included in buffer memory 102 and the plurality of fused 108A, including as many fuses as redundant rows, may be included.
However, with a large embedded memory, such as 256 Kb, the memory yield may still be low even when a memory with row and column redundancy is used. This is because if there are additional failures that are not corrected through redundancy, the entire die (silicon chip) may need to be discarded. Therefore, new and improved systems and methods are needed for reducing or correcting failures in memory devices in order to increase manufacturing yield.